1. Field of the Invention
The present invention relates to a booster circuit especially meant for generating a voltage of control of the word lines of a dynamic memory.
2. Discussion of the Related Art
FIG. 1 shows two cells of a dynamic memory associated with a conventional booster circuit. Each cell includes a capacitor 10 connected between a fixed potential, such as a low supply potential GND, and the source of a MOS-type N-channel access transistor 12. The drains of the transistors 12 are connected to respective bit lines BL. The gates of the access transistor 12 associated with the cells forming a word are connected to a common word line WL. A word line WL is generally selected via a P-channel MOS transistor 14, the gate of which is controlled by a word selection signal WS. The drain of transistor 14 is connected to word line WL and the source of this transistor receives a selection voltage Vpp.
When a 1 is written into a cell, supply voltage Vdd of the memory is presented on the corresponding bit line BL and transistor 14 is turned on. Voltage Vpp is thus presented, without any drop, on word line WL, whereby the access transistors 12 are turned on.
For a memory cell to be able to keep a value 1 as long as possible, capacitors 10 should be changed to the highest possible value, that is, to value Vdd of the supply voltage. Thus, voltage Vpp applied on the gates of transistors 12 must be higher than or equal to Vdd+Vt, where Vt is the gate-source threshold voltage of transistors 12. This is what the booster circuit enables to obtain.
The booster circuit of FIG. 1 includes a capacitor 16, a terminal of which is connected to ground GND and the other terminal of which, providing voltage Vpp, is connected to the cathodes of two diodes 18 and 19. The anodes of diodes 18 and 19 are connected to potential Vdd by two respective N-channel MOS transistors 21 and 22. The gate of transistor 22 is connected to the anode of diode 18, while the gate of transistor 21 is connected to the anode of diode 19. A capacitor 24 is connected between the anode of diode 18 and a terminal receiving a clock signal CK. A capacitor 25 is connected between the anode of diode 19 and a terminal receiving a clock signal CK*, complementary to signal CK.
Such a booster circuit supplies a voltage Vpp equal to 2Vdd-Vt in the steady state, value Vt being the threshold of diodes 18 and 19 which are generally formed of diode-connected MOS transistors.
During a first half clock period, signal CK is on zero and signal CK* is on 1 (at potential Vdd). The anode of diode 19, as indicated, is at a potential 2Vdd since capacitor 25 has been charged to Vdd during the preceding half-period. If the voltage of capacitor 16 is lower than 2Vdd-Vt, loads are transferred from capacitor 25 to capacitor 16 via diode 19, which tend to restore the voltage of capacitor 16 to 2Vdd-Vt.
Transistor 21 is on and is likely to provide, on its source, and thus on the anode of diode 18, a potential 2Vdd-Vt. The drain of transistor 21 being connected to potential Vdd, transistor 21 only provides, as indicated, potential Vdd to the anode of diode 18 and charges capacitor 24 to Vdd. The gate-source voltage of transistor 22 being negative, transistor 22 is nonconductive.
During the second half clock period, the states of the nodes are symmetrical, that is, signals CK and CK* and the anodes of transistors 18 and 19 are respectively on Vdd, 0, 2Vdd, and Vdd. Transistor 21 is then nonconductive and transistor 22 is on.
It appears that, in this booster circuit, as in other conventional booster circuits, such as that described in U.S. Pat. No. 5,406,523, the gates of N-channel MOS transistors receive a voltage which is substantially twice as high as the supply voltage of the circuit. This is unacceptable if it is desired to implement a dynamic memory in recent CMOS technologies, since the gate oxides are particularly thin and are likely to breakdown if the gate voltage exceeds the supply voltage of the circuit by a large amount. The breakdown risk essentially concerns N-channel MOS transistors since their substrate is connected to ground GND and the breakdown depends on the gate-substrate voltage. The problem is less critical for P-channel MOS transistors, the well of which can be freely connected to any potential.